The present invention relates in general to integrated circuits, and in particular to methods and circuitry for implementing delay-locking for two separate periodic signals using a single delay-locked loop circuit.
Delay-locked loops (DLLs) are commonly employed to generate a xe2x80x9ccleanxe2x80x9d internal clock signal from a noisy external clock signal. Among the factors by which the performance of a DLL is typically measured are the speed of operation (i.e., the minimum number of locking cycles), jitter, the size of the circuit and power consumption. There has been a need for more efficient implementation of DLLs as operating speeds of modern integrated circuits have increased. Some circuit applications require the use of two separate clock signals. For example, the so called double data rate (DDR) or quad data rate (QDR) synchronous dynamic random access memory (SDRAM) system uses a differential pair of clock signals, CLK and CLK#, to process data. These types of circuits have conventionally used two separate DLLs for the two clock signals. This implementation results in increased overall circuit size and power consumption, therefore increasing the cost of the device.
The present invention provides a significantly more efficient implementation of a DLL for systems using two separate clock signals, whereby a single DLL circuit is used to provide for locking of both clock signals. According to the present invention, the input to the DLL is controlled such that it responds to edges of both clock signals.
Accordingly, in one embodiment, the present invention provides a circuit receiving a first periodic signal CLK1 and a second periodic signal CLK2, there being a phase difference between CLK1 and CLK2, the circuit including a DLL having one delay path, wherein the same delay path provides delay tuning for both CLK1 and CLK2.
In another embodiment, the present invention provides a method of tuning the delay of two out-of-phase periodic signals, CLK1 and CLK2, including: combining CLK1 and CLK2 to generate a first periodic signal C_IN1 with a rising edge determined by CLK1 and a falling edge determined by CLK2; and applying C_IN1 to a DLL having a delay path that substantially maintains the duty ratio of C_IN1, whereby the delay-locked loop generates output signals that are delay-tuned to CLK1 and CLK2.
A better understanding of the nature and advantages of the present invention may be gained with reference to the following detailed description and the accompanying drawings.